The growing personal computer market is driving the demand for denser and denser Dynamic Random Access Memories (DRAM). Because high performance computers require wider and wider data buses, and because state of the art microprocessors typically employ a 32 bit or 64 bit data word, new generations of dense DRAMs are being organized with wide data paths of 32 bits (.times.32) or wider. A computer system using one of these microprocessors usually requires 4-8 MBytes (MB) of DRAM. 8 MB of memory for such a system, organized 2M by 32 can be made from four 16 Mb (2MX8) chips fairly simply. For example, a 2M by 32 Single In-line Memory Module (SIMM) would use 4 chips 2M by 8 in parallel. However, a 64 Mb chip organized 8M by 8 cannot be reconfigured so simply. Instead, a X32 SIMM organization from an 8M by 8 requires additional complex logic at a substantial loss in performance. However, a wide Input/Output (I/O) organization provides the optimum 64 Mb chip organization for use in a typical state of the art microprocessor based system, whether organized 2M by 32, 1M by 64 or 512K by 128. In fact, a 512k by 128 organization provides concurrent access to four 32 bit words simultaneously. Even as chip densities increase to 256 Mb and beyond, new wider word architectures, such as the Very Long Instruction Word (VLIW) architecture with instructions 256 bits wide or wider, are coming to the forefront.
Still another reason dense DRAM chips are tending toward a wide I/O DRAM organization is the performance requirement for DRAMs used by high performance microprocessors. Typical prior art DRAMs cannot meet this performance requirement. One state of the art approach to increasing Synchronous DRAM (SDRAM) throughput is known as "Prefetch". A Prefetch SDRAM has a wider on-chip data path than its off-chip I/O, e.g. 64 bit on-chip paths vs. 32 bit off-chip. All array (on-chip) operations occur simultaneously (i.e., 64 bit array reads and writes) with off chip transfers done sequentially, i.e. two 32 bit transfers. Consequently, because wide I/O RAMs simplify memory system design and improve RAM performance, wide I/O RAMs are needed.
However as the number of DRAM I/O increases, the number of chip pads and chip wiring between the DRAM circuits and from circuits to the pads must increase. Thus, chip size is also increased. In addition to the size of the main I/O bus, wiring RC delay in the peripheral circuits also becomes a concern in high density, wide I/O DRAMs. Still other timing problems such as address bus delay and timing skew become significant and are exacerbated further for DRAMs including redundancy.
FIG. 1 is a schematic representation of a DRAM chip 100 with a prior art single global bus 102 for addresses, I/O and External Chip Controls, e.g., RAS, CAS, SEL, etc. To reduce wiring RC delay with such a bus, the bus must be fragmented, adding, thereby, extra buffers (represented by arrow heads 104) and forming local busses 106. Since neither the global bus 102 nor the local buses 106 can share the same wiring channels with each other or, with the main Read/Write Data lines (RWD), not shown, this approach requires an even larger (wider) bus area. The RWD lines are lines between the memory units 108 and the off chip driver/receiver (DQ) at each Data pad 112. A wider bus means a wider chip and incurs significant wiring congestion from, for instance cross pad connections. A global bus of addresses and array control signals must be along the entire length of the chip to access the memory cells in every unit 108 of the memory chip 100.
This prior art structure is simple yet difficult to implement because it requires complicated wiring 110 across the pads 112. It is impossible to connect redundancy circuits (which number in the thousands) directly to such a bus. If the DRAM includes redundancy circuits, local buses are necessary. Thus, there are effectively three parallel address buses on this prior art chip.
Normally, the long global bus 102 has large RC delay, especially when redundancy circuits are attached directly to it. A 0.5 RC delay on such heavily loaded lines is larger than 1ns from center to edge. However, the RC delay can be reduced either by widening the mutual lines or by segmentation plus redrive, i.e., duplicated bus lines carry signals to the segment redrive circuits. Both of these approaches increase chip size. Therefore, a bus arrangement is needed that minimizes bus delay and skew is needed.